1. Field of the Invention
The present invention relates to a method of fabricating a memory device. More particularly, the present invention relates to a method for fabricating a mask ROM.
2. Description of the Related Art
As the power of the microprocessor becomes stronger and the operation complexity of software increases, the requirement for memory grows. Therefore, it is now the most important task of semiconductor manufacturers to fabricate low cost and high-density memories. Memories can be divided into two categories: read only memory (ROM) and random access memory (RAM). ROM includes mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM) and electrically erasable programmable ROM (EEPROM).
Currently, the most commonly used type of ROM device is called an electrically erasable programmable ROM (EEPROM). The EEPROM device allows data or programs to be erased or written bit by bit. Data can be repeatedly read, written, and erased several times. Recently, data access speeds of 70 to 80 ns have been achieved, in what is called a flash memory by Intel. The flash memory has a structure similar to the structure of an EPROM device. The data or programs are erased or written block by block. Only one or two seconds are necessary to complete an erasure. This can save a lot of time and results in a lower fabrication cost.
RAM includes static random access memory (SRAM) and dynamic random access memory (DRAM).
Usually, ROM uses channel transistors as memory cells. During programming, dopants are selectively implanted into certain channel regions to modify the threshold voltage and to turn memory cells ON/OFF. ROM includes polysilicon word lines crossing bit lines. The channel of a memory cell is below a word line and between two bit lines. The implantation of ions into the channel determines the binary data "0" or "1".
As the size of semiconductor devices decreases to below 0.6 .mu.m, a plug ion implantation process must be performed between the step of forming a contact opening in the inter-layer dielectric layer and the step of forming a contact plug in the inter-layer dielectric layer to prevent a junction leakage effect and a spiking effect, which occur at the junction of the contact opening and the source/drain region.
FIG. 1A is a schematic, top view of a mask ROM.
Referring to FIGS. 1A and 1B, a gate oxide layer 102 is formed on a p-type substrate 100. Gates 104 are formed over the substrate 100 as word lines. An ion implantation process is performed by using gates 104 as masks to form n-type source/drain regions as bit lines. The bit lines cross the word lines perpendicularly. Channels are formed below the word lines. The state of each memory cell is determined by the channels. The method of closing the channels is to implant p-type ions into specific channels 107 to form code ion implant regions 110.
FIGS. 1B through 1E are schematic, cross-sectional diagrams used to depict steps in a conventional method for fabricating a mask ROM.
Referring to FIG. 1B, a p-type substrate 100 is provided. An isolation region 101 is formed in the substrate 100. A gate oxide layer 102 and gates 104 are formed in sequence on the substrate 100.
An ion implantation process is performed by using n-type ions as dopants to form a plurality of source/drain regions 106 in the substrate 100. Channels 107 are formed between two adjacent source/drain regions 106.
Referring to FIG. 1C, a patterned photoresist layer 108 is formed over the substrate 100 to expose subsequently formed code ion implant regions. An ion implantation process is performed by using phosphorus-31 as a dopant. The implantation energy is 160 KeV and the dosage of the dopant is about 1.times.10.sup.14 ions/cm.sup.2. After performing an annealing process at 850.degree. C., code ion implant regions 110 are formed. The photoresist layer 108 is removed.
Referring to FIG. 1D, a borophosphosilicate glass layer 112 is formed over the substrate 100 by chemical vapor deposition. A flow process is performed to planarize the borophosphosilicate glass layer 112.
A photoresist layer 118 is formed on the borophosphosilicate glass layer 112. A contact opening 120 is formed in the borophosphosilicate glass layer 112 to expose a portion of the source/drain region 106a.
An ion implantation process is performed by using phosphorus-31 as a dopant. The implantation energy is 70 KeV and the dosage of the dopants is about 2.times.10.sup.15 ions/cm.sup.2. A reflow process is performed at 850.degree. C. A plug ion implant region 122 is formed in the source/drain region 106a.
Referring to FIG. 1E, a barrier layer 124 is formed in the contact opening 120. A contact plug 126 is formed in the contact opening 120 to electrically couple with the plug ion implant region 122 located in the source/drain region 106a.
As the size of semiconductor devices decreases to below 0.6 .mu.m, a plug ion implantation process must be performed after the code ion implantation process. This means that at least two ion implantation processes are performed in the conventional process. The manufacturing time is long and the manufacturing costs are high.